Method of designing semiconductor integrated circuit, designing apparatus, semiconductor integrated circuit system, semiconductor integrated circuit mounting substrate, package and semiconductor integrated circuit

ABSTRACT

To provide a method of designing a semiconductor integrated circuit with a high workability also in an increase in a scale of an LSI and an enhancement in an integration and designing a semiconductor integrated circuit system in which an unnecessary radiation is reduced and which is excellent in a heat characteristic, a reverse design flow to that in the conventional art is implemented, and a mounting substrate such as a printed-circuit board is first designed and a package substrate for mounting an LSI is designed based on a result of the design of the mounting substrate, and a layout design of the LSI to be mounted on the package substrate is then carried out.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method of designing a semiconductorintegrated circuit, a designing apparatus, a semiconductor integratedcircuit system, a semiconductor integrated circuit mounting substrate, apackage and a semiconductor integrated circuit, and more particularly toa method of designing a semiconductor integrated circuit system whichdesigns a semiconductor integrated circuit and reduces an unnecessaryradiation (EMI: Electromagnetic Interference), and furthermore, isexcellent in a heat characteristic in consideration of a mounting statebased on a result of a design of a mounting substrate constituting thesemiconductor integrated circuit system.

2. Description of the Related Art

A semiconductor integrated circuit (LSI) has a utilization rangeenlarged to communicating apparatuses such as a cell phone, generaldomestic articles, toys and cars in addition to a computer. On the otherhand, however, there is a problem in that an unnecessary radiationgenerated from these products causes a radio interference of a receivingdevice such as a television or a radio and a malfunction of othersystems. A countermeasure for the whole products, for example, filteringor shielding is also taken against the problem. However, it is hard totake the countermeasure in respect of an increase in the number ofcomponents, an increase in a cost and the difficulty of a countermeasureto be taken against the product. In the situations, there has beengreatly demanded a noise suppression of an LSI system including an LSIpackage and a mounting substrate mounting the LSI package.

Under the circumstances, the LSI system is positioned as a key device ineach product and an increase in a scale and a speed of the LSI systemhas been required for maintaining a competitive power of the product.While a product cycle is shortened, it is necessary to automate an LSIsystem design in order to meet these requirements and various studieshave been made.

Under present conditions, however, a design flow is usually determined,that is, an LSI is first designed and a package is designedcorresponding to the LSI, and a mounting substrate for mounting thepackage is then designed. In other words, a layout design of the LSI isfirst carried out and the package is designed corresponding to thelayout design of the LSI. Then, the LSI is disposed on the mountingsubstrate corresponding to an arrangement of an external connectingterminal of the package and a layout design of a wiring pattern to beconnected to the external connecting terminal is carried out.

For example, as shown in FIG. 56, a step (S9001) of investigating asystem and a specification is executed and an LSI is then designed basedon the specification (S9004), and a step of designing a package (S9003)is thereafter executed corresponding to the layout design of the LSI.Subsequently, an arrangement of the LSI on the mounting substrate and alayout design of a wiring pattern to be connected to an externalconnecting terminal are executed corresponding to the arrangement of theexternal connecting terminal of the package (a design of the mountingsubstrate for mounting the package: S9002).

In the LSI design, there is no information about the design of thepackage and the mounting substrate. Therefore, a consideration cannot betaken and there is a drawback that an intersection of the wiring on thepackage substrate is caused and a wiring length is increased. For thisreason, in some cases, it is necessary to carry out a feedback, that is,the package designing step (S9003) is executed and an input/output pad(I/O) is then disposed again (S9006), and the processing returns to theLSI designing step (S9004), or the mounting substrate designing step(S9002) is executed and the external connecting terminal of the packageis then disposed again (S9007), and the processing returns to thepackage designing step (S9003).

Therefore, there has been proposed a substrate designing apparatus foranalyzing a signal when carrying out a substrate layout design in orderto decrease a retracing work such as a revision of a design (PatentDocument 1).

Patent Document 1: JP-A-11-353339 Publication

However, an LSI design is also carried out corresponding to the internalcondition of an LSI and an arrangement of an I/O terminal is alsodetermined by the apparatus described in the Patent Document 1. In theLSI design, there is no layout information about a mounting substrate.For this reason, it is also hard to carry out a design without afeedback.

A scale and an integration of the LSI are continuously increased. Thereis a problem in that a circuit design of the LSI becomes complicated,and furthermore, the number of external connecting terminals isincreased and it is hard to correspond to a change into a multibit withthe increase in the scale and integration of the LSI.

Moreover, an arrangement of a signal wiring becomes complicated. Forthis reason, there is also a problem in that an unnecessary radiation(EMI) analysis and a thermal analysis become complicated, and it is hardto carry out a perfect automation in an optimization of the design, anda manual correction is required, resulting in an increase in a timerequired for a development.

SUMMARY OF THE INVENTION

In consideration of the actual conditions, it is an object of theinvention to provide a semiconductor integrated circuit system which candesign a semiconductor integrated circuit, a package and a mountingsubstrate with a high workability also in an increase in a scale and anintegration of an LSI, can reduce an unnecessary radiation and isexcellent in a heat characteristic.

Therefore, the invention is characterized in that a reverse design flowto that in the conventional art is implemented, and a mounting substratesuch as a printed-circuit board is first designed and a packagesubstrate mounting an LSI is designed based on a result of the design ofthe mounting substrate, and a layout design of the LSI to be mounted onthe package substrate is then carried out.

For example, a position of an external connecting terminal of thepackage is investigated based on information about an arrangement ofcomponents on the mounting substrate, and an arrangement of aninput/output terminal of the LSI is determined in consideration of theposition of the external connecting terminal of the package substrate.More specifically, by optimizing the arrangement of the input/outputterminal of the LSI based on information about the mounting substrateand the package substrate in place of the internal condition of the LSI,it is possible to execute a whole optimization of the mountingsubstrate, the package substrate and the LSI.

Moreover, an optimum arrangement of the mounting substrate and a signalwiring of the package substrate are also taken into consideration.Therefore, it is possible to eliminate a drawback such as anintersecting structure or an increase in a wiring length, therebyenhancing quality.

Furthermore, a complicated arrangement of the signal wiring is notgenerated. Therefore, it is possible to reduce a man-hour and tocorrespond to an automation.

More specifically, the invention provides a method of designing asemiconductor integrated circuit system comprising the steps ofdesigning a mounting substrate constituting the system based on systemspecification information, designing a semiconductor integrated circuitpackage including a package substrate to be mounted on the mountingsubstrate based on a result of the design obtained at the step ofdesigning a mounting substrate, and designing a semiconductor integratedcircuit to be mounted on the semiconductor integrated circuit package inorder to determine an I/O terminal position of the semiconductorintegrated circuit based on a result of the design obtained at the stepof designing a semiconductor integrated circuit package.

According to the method, in the design of the semiconductor integratedcircuit system, first of all, a mounting substrate such as aprinted-circuit board is designed, and a design is carried out from adownstream side toward an upstream side, that is, toward the packagesubstrate design and an LSI design therefrom. In the design of themounting substrate, a rough position of a terminal array of the packageis determined by setting, as input data, information such as a result ofa component arrangement which is obtained based on the systemspecification information. Therefore, it is possible to suppress anintersection of a wiring and an increase in a wiring length. Also in anincrease in a scale and a speed and a change into a multibit in thesemiconductor integrated circuit system, it is possible to reduce thecomplicated arrangement of the signal wiring. Accordingly, it ispossible to easily automate the wiring.

Moreover, the invention provides the method of designing a semiconductorintegrated circuit system, wherein the semiconductor integrated circuitpackage includes a package substrate having a grid array terminalstructure in which external connecting terminals are arranged like agrid.

Furthermore, the invention provides the method of designing asemiconductor integrated circuit system, wherein the mounting substratedesigning step comprises the steps of dividing, into a plurality ofregions, a region including the semiconductor integrated circuit to be adesign target and a device which is previously designed therearound, andcontrolling a wiring in order to complete the wiring in the region.

According to the structure, the wiring is controlled in such a mannerthat the wiring is completed in the region. Therefore, it is possible toform a semiconductor integrated circuit system which can easily beautomated, does not include an intersecting region and can carry out ahigh speed driving operation.

In addition, the invention provides a method of designing asemiconductor integrated circuit mounting substrate mounting a packagesubstrate loading a semiconductor integrated circuit chip andconstituting a desirable system, comprising the step of designing asemiconductor integrated circuit mounting substrate by setting a systemspecification as input data.

Moreover, the invention provides the method of designing a semiconductorintegrated circuit mounting substrate, wherein a mounting substratehaving a wiring pattern for connecting a semiconductor integratedcircuit (chip) loaded on the package substrate is designed prior to adesign of the semiconductor integrated circuit chip.

Furthermore, the invention provides the method of designing asemiconductor integrated circuit mounting substrate, wherein the step ofdesigning a semiconductor integrated circuit mounting substratedetermines a virtual wiring leading point in a position placed apartfrom an outer edge of the package substrate by a predetermined distanceand carrying out a design in such a manner that the wiring patternpasses through the wiring leading point.

In addition, the invention provides the method of designing asemiconductor integrated circuit mounting substrate, wherein the step ofdesigning a mounting substrate comprises the step of dividing a regionincluding a semiconductor integrated circuit to be a design targetdevice and a device which is previously designed therearound.

Moreover, the invention provides the method of designing a semiconductorintegrated circuit mounting substrate, wherein the step of designing amounting substrate comprises the step of designing the wiring leadingpoint in such a manner that a line connecting an input/output pad of asemiconductor integrated circuit to be a design target device, aninternal connecting terminal for a connection, to the input/output pad,of the package substrate to be connected to the input/output pad, anexternal connecting terminal to be connected to the mounting substrateof the package substrate, and the wiring leading point does not have anintersecting region.

Furthermore, the invention provides a method of designing a packagesubstrate loading a semiconductor integrated circuit (chip) andconstituting a desirable system on a semiconductor integrated circuitmounting substrate, wherein input data at the step of designing apackage substrate include a design result of the step of designing asemiconductor integrated circuit mounting substrate.

In addition, the invention provides the method of designing a packagesubstrate, wherein the step of designing a package substrate comprisesthe step of carrying out a design in such a manner that a wiringconstituting a signal group corresponding to the component is arrangedin a region divided depending on a position on the semiconductorintegrated circuit mounting substrate in which a component is disposed.

By the structure, the wiring constituting the signal group correspondingto the component is disposed in the region divided depending on theposition on the semiconductor integrated circuit mounting substrate inwhich the component is arranged. Therefore, a wiring length can bereduced and a speed can be increased.

Moreover, the invention provides the method of designing a packagesubstrate, wherein the step of designing a package substrate comprisesthe step of constituting a package substrate which includes at least onepower plane and in which the power plane is divided into a plurality ofregions for each power unit in order to correspond to a power divisionon the mounting substrate.

Furthermore, the invention provides the method of designing a packagesubstrate, wherein the step of designing a package substrate comprisesthe step of connecting, to a power plane, any of a plurality ofconductor layers which is positioned on a surface layer mounting an LSIin such a manner that the conductor layer includes a power ring and awiring in the package substrate does not have an intersecting regionthrough the power ring.

In addition, the invention provides the method of designing a packagesubstrate, wherein the step of designing a package substrate comprisesthe step of carrying out a design in such a manner that a wiring in thepackage substrate does not have an intersecting region based onconnecting information from a semiconductor integrated circuit to be atarget to a peripheral component of the semiconductor integratedcircuit.

Moreover, the invention provides the method of designing a packagesubstrate, wherein the step of designing a package substrate comprisesthe step of carrying out a design in order to divide a plane of thepackage substrate into N regions and to complete a signal wiring foreach of the regions.

Furthermore, the invention provides the method of designing a packagesubstrate, wherein the step of designing a package substrate comprisesthe step of carrying out a design in such a manner that an externalconnecting terminal of the package substrate constitutes a ball gridarray (BGA) and an external connecting terminal forming plane is dividedinto N regions, and a signal wiring is completed for each of theregions.

In addition, the invention provides the method of designing a packagesubstrate, wherein the step of designing a package substrate comprisesthe step of carrying out a design in such a manner that the externalconnecting terminal forming plane is divided into the N regions and thesignal wiring is completed for each of the regions corresponding to anarrangement of a component on the semiconductor integrated circuitmounting substrate.

Moreover, the invention provides the method of designing a packagesubstrate, wherein the N is four.

Furthermore, the invention provides the method of designing a packagesubstrate, wherein the N is eight.

In addition, the invention provides the method of designing a packagesubstrate, wherein the step of designing a package substrate comprisesthe step of carrying out a design in such a manner that grouping isperformed corresponding to an array of the external connecting terminaland a signal wiring is adjacent every group.

More specifically, the signal group is divided into groups depending onthe array of the external connecting terminal of the package substrateand the signal wiring is designed adjacently to each group.Consequently, it is possible to easily carry out a swap by only changinga connection in the group.

Moreover, the invention provides the method of designing a packagesubstrate, wherein the step of designing a package substrate comprisesthe step of carrying out a design in such a manner that a line of theexternal connecting terminal is connected to an adjacent input/outputpad of the semiconductor integrated circuit to be loaded on the packagesubstrate.

Furthermore, the invention provides the method of designing a packagesubstrate, comprising the step of carrying out a design in such a mannerthat the package substrate includes at least three conductor layers of asurface layer wiring, a power plane layer and a lowermost layer wiring,and the surface layer wiring and the lowermost layer wiring have aformation prohibiting region.

In addition, the invention provides the method of designing a packagesubstrate, further comprising the step of carrying out a design in sucha manner that the surface layer wiring and the lowermost layer wiringhave a formation prohibiting region having a predetermined width from anend in the divided region.

Moreover, the invention provides a method of designing a semiconductorintegrated circuit mounting a semiconductor integrated circuit chip on apackage substrate and constituting a desirable system on a semiconductorintegrated circuit mounting substrate, wherein the step of designing asemiconductor integrated circuit comprises the step of determining aninput/output pad arrangement by setting, as input data, a result of thedesign obtained at the step of designing a semiconductor integratedcircuit mounting substrate.

Furthermore, the invention provides the method of designing asemiconductor integrated circuit, wherein the step of designing asemiconductor integrated circuit comprises the step of carrying out amodification in consideration of an internal condition of an LSI afterthe step of determining an input/output pad arrangement, and the step ofcarrying out a modification in consideration of the internal conditionof the LSI to be modified.

In addition, the invention provides the method of designing asemiconductor integrated circuit, further comprising the step ofdesigning the arrangement of the input/output pad of the semiconductorintegrated circuit corresponding to an arrangement of an externalconnecting terminal of the package substrate.

Moreover, the invention provides the method of designing a semiconductorintegrated circuit, wherein the designing step comprises the step ofcarrying out a design in such a manner that a line of the externalconnecting terminal is connected to an adjacent input/output pad of thesemiconductor integrated circuit.

Furthermore, the invention provides the method of designing asemiconductor integrated circuit, further comprising the step ofdesigning an arrangement of the input/output pad of the semiconductorintegrated circuit corresponding to an arrangement of a component of thesemiconductor integrated circuit mounting substrate.

In addition, the invention provides the method of designing asemiconductor integrated circuit, wherein the designing step comprisesthe step of carrying out a design in such a manner that a wiring fromthe semiconductor integrated circuit mounting substrate to theinput/output pad of the semiconductor integrated circuit does not havean intersecting region.

Moreover, the invention provides the method of designing a semiconductorintegrated circuit, further comprising the step of carrying out a designin order to determine a driving capability of an input/output cell to beconnected to the input/output pad of the semiconductor integratedcircuit corresponding to an arrangement of a component of thesemiconductor integrated circuit mounting substrate.

In the invention, furthermore, there are provided the steps of designinga mounting substrate constituting the system based on systemspecification information, designing a semiconductor integrated circuitpackage including a package substrate to be mounted on the mountingsubstrate based on a design result obtained at the step of designing amounting substrate, and designing a semiconductor integrated circuit tobe mounted on the semiconductor integrated circuit package in order todetermine an I/O terminal position of the semiconductor integratedcircuit based on a design result obtained at the step of designing asemiconductor integrated circuit package, wherein the step of designinga mounting substrate serves to carry out a design in consideration of aminimum semiconductor integrated circuit design restriction.

The invention provides an apparatus for designing a semiconductorintegrated circuit system comprising a mounting substrate designingportion for designing a mounting substrate constituting the system basedon system specification information, a package designing portion fordesigning a semiconductor integrated circuit package including a packagesubstrate to be mounted on the mounting substrate based on a designresult obtained by the mounting substrate designing portion, and asemiconductor integrated circuit designing portion for designing asemiconductor integrated circuit to be mounted on the semiconductorintegrated circuit package in order to determine an I/O terminalposition of the semiconductor integrated circuit based on a designresult obtained by the package designing portion.

The invention provides the apparatus for designing a semiconductorintegrated circuit system, wherein the semiconductor integrated circuitpackage includes a semiconductor integrated circuit package having agrid array terminal structure in which external connecting terminals arearranged like a grid.

Furthermore, the invention provides the apparatus for designing asemiconductor integrated circuit system, wherein the mounting substratedesignating portion includes a region dividing portion for dividing,into a plurality of regions, a region including the semiconductorintegrated circuit to be a design target and a device which ispreviously designed therearound, and a wiring control portion forcontrolling a wiring in such a manner that a wiring is completed in aregion divided by the region dividing portion.

In addition, the invention provides an apparatus for designing asemiconductor integrated circuit mounting substrate mounting a packagesubstrate loading a semiconductor integrated circuit and constituting adesirable system, comprising a mounting substrate designing portion fordesigning a semiconductor integrated circuit mounting substrate bysetting a system specification as input data.

Moreover, the invention provides the apparatus for designing asemiconductor integrated circuit mounting substrate, wherein themounting substrate designing portion includes a semiconductor integratedcircuit mounting substrate constituted to use, as input data, systemspecification information which does not include design information of asemiconductor integrated circuit chip.

In the invention, furthermore, the mounting substrate designing portionincludes a designing portion for determining a virtual wiring leadingpoint in a position placed apart from an outer edge of the packagesubstrate by a predetermined distance and carrying out a design in sucha manner that the wiring pattern passes through the wiring leadingpoint.

In addition, the invention provides the apparatus for designing asemiconductor integrated circuit mounting substrate, wherein themounting substrate designing portion includes a dividing control portionfor dividing a region including a semiconductor integrated circuit to bea design target device and a device which is previously designedtherearound, and a control portion for carrying out a control tocomplete a wiring in the divided region.

Moreover, the invention provides the apparatus for designing asemiconductor integrated circuit mounting substrate, wherein themounting substrate designing portion includes an intersecting controlportion for designing a wiring leading point in such a manner that aline connecting an input/output pad of a semiconductor integratedcircuit to be a design target device, an internal connecting terminalfor a connection, to the input/output pad, of the package substrate tobe connected to the input/output pad, an external connecting terminal tobe connected to the mounting substrate of the package substrate, and thewiring leading point does not have an intersecting region.

In addition, the invention provides an apparatus for designing a packagesubstrate loading a semiconductor integrated circuit chip andconstituting a desirable system on a semiconductor integrated circuitmounting substrate, wherein input data of the package substratedesigning apparatus include a design result of the semiconductorintegrated circuit mounting substrate designing portion.

Moreover, the invention provides the apparatus for designing a packagesubstrate, further comprising a dividing control portion for carryingout a division every signal group in such a manner that a wiringconstituting a signal group corresponding to the component is disposedin a divided region depending on a position on the semiconductorintegrated circuit mounting substrate in which a component is arranged.

Furthermore, the invention provides the apparatus for designing apackage substrate, wherein the dividing control portion carries out adesign to divide a plane of the package substrate into N regions and tocomplete a signal wiring for each of the regions.

In addition, the invention provides the apparatus for designing apackage substrate, wherein the dividing control portion carries out adesign in such a manner that an external connecting terminal of thepackage substrate constitutes a ball grid array, and an externalconnecting terminal forming plane is divided into N regions and a signalwiring is completed for each of the regions.

Moreover, the invention provides the apparatus for designing a packagesubstrate, wherein the dividing control portion carries out a design todivide the external connecting terminal forming plane into the N regionsand to complete the signal wiring for each of the regions correspondingto an arrangement of a component on the semiconductor integrated circuitmounting substrate.

Furthermore, the invention provides the apparatus for designing apackage substrate, wherein the N is four.

In addition, the invention provides the apparatus for designing apackage substrate, wherein the N is eight.

Moreover, the invention provides the apparatus for designing a packagesubstrate, wherein the dividing control portion has such a structurethat grouping is performed corresponding to an array of the externalconnecting terminal and a signal wiring is adjacent every group.

Furthermore, the invention provides the apparatus for designing apackage substrate, wherein the dividing control portion has such astructure that a line of the external connecting terminal is connectedto an adjacent input/output pad of the semiconductor integrated circuitto be loaded on the package substrate.

In addition, the invention provides the apparatus for designing apackage substrate, wherein the package substrate includes at least onepower plane and a power plane dividing portion for dividing the powerplane into a plurality of regions for each power unit in order tocorrespond to a power division on the mounting substrate.

Moreover, the invention provides the apparatus for designing a packagesubstrate, further comprising a power control portion in which any ofthe conductor layers which is positioned on a surface layer mounting anLSI includes a power ring and a wiring in the package substrate isconnected to the power plane through the power ring so as not to have anintersecting region.

Furthermore, the invention provides the apparatus for designing apackage substrate, wherein a connection is included in such a mannerthat a wiring in the package substrate does not have an intersectingregion based on connecting information from a semiconductor integratedcircuit to be a target to a peripheral component of the semiconductorintegrated circuit.

In addition, the invention provides the apparatus for designing apackage substrate, further comprising a dividing control portion forcarrying out a design to divide a plane of the package substrate intofour regions and to complete a signal wiring for each of the regions.

Moreover, the invention provides the apparatus for designing a packagesubstrate, further comprising a dividing control portion for carryingout a design in such a manner that an external connecting terminal ofthe package substrate constitutes a ball grid array, an externalconnecting terminal forming plane is divided into four regions and asignal wiring is completed for each of the regions.

Furthermore, the invention provides the apparatus for designing apackage substrate, further comprising a dividing control portion forcarrying out a design to divide a plane of the package substrate intoeight regions and to complete a signal wiring for each of the regions.

Moreover, the invention provides the apparatus for designing a packagesubstrate, further comprising a dividing control portion for carryingout a design in such a manner that an external connecting terminal ofthe package substrate constitutes a ball grid array, an externalconnecting terminal forming plane is divided into, eight regions and asignal wiring is completed for each of the regions.

Moreover, the invention provides the apparatus for designing a packagesubstrate, further comprising a signal group dividing control portionfor carrying out a design in such a manner that the signal group isdivided every region.

Furthermore, the invention provides the apparatus for designing apackage substrate, wherein the package substrate includes at least threeconductor layers of a surface layer wiring, a power plane layer and alowermost layer wiring, and the surface layer wiring and the lowermostlayer wiring include a wiring control portion for carrying out a controlto have a formation prohibiting region.

In addition, the invention provides the apparatus for designing apackage substrate, wherein the wiring control portion serves to carryout a control in such a manner that the surface layer wiring and thelowermost layer wiring have a formation prohibiting region having apredetermined width from an end in the divided region.

Moreover, the invention provides an apparatus for designing asemiconductor integrated circuit mounting a semiconductor integratedcircuit on a package substrate and constituting a desirable system on asemiconductor integrated circuit mounting substrate, comprising a datainput portion for determining an input/output pad arrangement by settinga design result of a semiconductor integrated circuit mounting substrateas input data.

Furthermore, the invention provides the apparatus for designing asemiconductor integrated circuit, further comprising an internalcondition considering portion for determining an input/output padarrangement by setting the design result of the semiconductor integratedcircuit mounting substrate as input data and carrying out a modificationin consideration of an internal condition of an LSI, and a correctingportion for correcting the input/output pad arrangement by setting anoutput of the modifying portion as input data.

In addition, the invention provides the apparatus for designing asemiconductor integrated circuit, further comprising an input/output padarranging portion for designing the arrangement of the input/output padof the semiconductor integrated circuit corresponding to an arrangementof an external connecting terminal of the package substrate.

Moreover, the invention provides the apparatus for designing asemiconductor integrated circuit, further comprising an input/output padarranging portion for designing the arrangement of the input/output padof the semiconductor integrated circuit corresponding to an arrangementof a component of the semiconductor integrated circuit mountingsubstrate.

Furthermore, the invention provides the apparatus for designing asemiconductor integrated circuit, further comprising an input/outputcell designing portion for determining a driving capability of aninput/output cell to be connected to the input/output pad of thesemiconductor integrated circuit corresponding to an arrangement of acomponent of the semiconductor integrated circuit mounting substrate.

In addition, the invention provides an apparatus for designing asemiconductor integrated circuit system comprising a mounting substratedesigning portion for designing a mounting substrate constituting thesystem based on system specification information, a package designingportion for designing a semiconductor integrated circuit (LSI) packageincluding a package substrate to be mounted on the mounting substratebased on a design result obtained by the mounting substrate designingportion, and a semiconductor integrated circuit designing portion fordesigning a semiconductor integrated circuit to be mounted on thesemiconductor integrated circuit package in order to determine an I/Oterminal position of the semiconductor integrated circuit based on adesign result obtained by the semiconductor integrated circuit packagedesigning portion, wherein the mounting substrate designing portion hassuch a structure as to carry out a design in consideration of a minimumsemiconductor integrated circuit design restriction.

Moreover, the invention provides a semiconductor integrated circuitsystem in which a semiconductor integrated circuit mounted on a packagesubstrate is loaded on a mounting substrate having a wiring formedthereon together with an electronic component and a circuit connectionis thus carried out, wherein an external connecting terminal of thepackage substrate to be connected to a wiring on the mounting substratefrom the wiring and a conductive path reaching an input/output pad ofthe semiconductor integrated circuit through the wiring of the packagesubstrate are constituted so as not to have an intersecting region.

In the invention, furthermore, a wiring on the mounting substrate isstraight and parallel in such a manner that almost mutual intervals arealmost constant in a region having a predetermined width from an outeredge of the package substrate of the semiconductor integrated circuit,and is disposed irregularly on an outside of the region.

In addition, the invention provides a semiconductor integrated circuitmounting substrate comprising a wiring pattern mounting and connecting,together with an electronic component, a semiconductor integratedcircuit loaded on a package substrate, wherein the wiring pattern passesthrough a wiring leading point formed virtually in a position placedapart from an outer edge of the package substrate by a predetermineddistance.

Moreover, the invention provides the semiconductor integrated circuitmounting substrate, wherein the wiring pattern is disposed in dividedregions formed by dividing a region including a semiconductor integratedcircuit to be a design target device and a device which is previouslydesigned therearound, respectively.

Furthermore, the invention provides the semiconductor integrated circuitmounting substrate, wherein a wiring connected is carried out in such amanner that a line connecting an input/output pad of a semiconductorintegrated circuit to be a design target device, an internal connectingterminal for a connection, to the input/output pad, of the packagesubstrate to be connected to the input/output pad, an externalconnecting terminal to be connected to the mounting substrate of thepackage substrate, and the wiring leading point does not have anintersecting region.

In addition, the invention provides a package substrate mounting asemiconductor integrated circuit, connected to a semiconductorintegrated circuit mounting substrate including a wiring patterntogether with an electronic component, and constituting a semiconductorintegrated circuit system, wherein a wiring constituting a signal groupcorresponding to the component is arranged in a region divided dependingon a position on the semiconductor integrated circuit mounting substratein which a component is disposed.

Moreover, the invention provides the package substrate, wherein thepackage substrate includes at least one power plane and the power planeis divided into a plurality of regions for each power unit in order tocorrespond to a power division on the mounting substrate.

Furthermore, the invention provides the package substrate, wherein thepackage substrate includes a plurality of conductor layers, and any ofthe conductor layers which is positioned on a surface layer mounting anLSI includes a power ring and a wiring in the package substrate isconnected to the power plane through the power ring so as not to have anintersecting region.

In addition, the invention provides the package substrate, wherein thepackage substrate has such a structure that a wiring in the packagesubstrate does not have an intersecting region based on connectinginformation from a semiconductor integrated circuit to be a target to aperipheral component of the semiconductor integrated circuit.

Moreover, the invention provides the package substrate, wherein a planeof the package substrate is divided into N regions and a signal wiringis formed to be completed for each of the regions.

Furthermore, the invention provides the package substrate, wherein anexternal connecting terminal of the package substrate constitutes a ballgrid array, and an external connecting terminal forming plane is dividedinto N regions and a signal wiring is completed for each of the regions.

In addition, the invention provides the package substrate, wherein the Nis four.

Moreover, the invention provides the package substrate, wherein the N iseight.

Furthermore, the invention provides the package substrate, wherein thepackage substrate is designed in such a manner that grouping isperformed corresponding to an array of the external connecting terminaland a signal wiring is adjacent in each group.

By the structure, it is possible to easily implement a replacement ofthe terminal in the group, that is, a swap thereof.

In addition, the invention provides the package substrate, wherein thepackage substrate is designed in such a manner that a line of theexternal connecting terminal is connected to an adjacent input/outputpad of the semiconductor integrated circuit to be loaded on the packagesubstrate.

Moreover, the invention provides the package substrate, wherein thepackage substrate includes at least three conductor layers of a surfacelayer wiring, a power plane layer and a lowermost layer wiring, and thesurface layer wiring and the lowermost layer wiring are formed to keepaway from a region having a predetermined width from an end of thedivided region, and the power plane layer maintains a current path inthe region having the predetermined width from the end in the dividedregion.

Furthermore, the invention provides the package substrate, wherein thelowermost layer wiring constitutes a ball to be an external connectingterminal and the surface layer wiring is provided with a bond fingerincluding a bond portion formed like a band along a peripheral edge ofthe semiconductor integrated circuit and a finger portion extended to aposition placed just above the external connecting terminal to beconnected from the bond portion, and a tip of the bond finger isconnected to the corresponding external connecting terminal through avia formed thereon.

In addition, the invention provides the package substrate, wherein thebond finger is formed in two lines and a direction of the extension ofthe finger portion is set apart from the bond portion, and the externalconnecting terminal and the semiconductor integrated circuit areconnected to each other through a detour using the lowermost layerwiring.

Moreover, the invention provides a semiconductor integrated circuitmounted on a package substrate and constituting a desirable system on asemiconductor integrated circuit mounting substrate, wherein theinput/output pad is arranged every group so as to be disposed closest toan external connecting terminal of the package substrate, and at leasttwo input/output pads which are juxtaposed are arranged to be connectedto the external connecting terminal juxtaposed in an orthogonaldirection to a direction of the juxtaposition.

In the invention, the grouping is carried out by using, as the signalgroup, two concepts having the signal group corresponding to thecomponent on the semiconductor integrated circuit mounting substrate andthe signal group corresponding to the external connecting terminal arrayof the package. The former is the signal group for a circuit connectionand the latter is the grouping in accordance with the physical array ofthe external connecting terminal, and they are to be considered asindependent events, respectively. While the former is a comparativelylarge division, the latter is a division into small groups, for example,three or four lines.

According to the structure, the semiconductor integrated circuit isdesigned to have the input/output terminal corresponding to thesemiconductor integrated circuit mounting substrate and the package (thepackage substrate) in consideration of an unnecessary radiatingcharacteristic and a heat characteristic of the semiconductor integratedcircuit including the semiconductor integrated circuit mountingsubstrate and the package (the package substrate). Therefore, it ispossible to provide a semiconductor integrated circuit system in which aspeed of the design can be increased and the unnecessary radiatingcharacteristic and the heat characteristic are excellent.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a flowchart showing a method of designing a semiconductorintegrated circuit system according to a first embodiment of theinvention,

FIG. 2 is a diagram showing an apparatus for designing a semiconductorintegrated circuit system according to the first embodiment of theinvention,

FIG. 3 is a flowchart showing the method of designing a semiconductorintegrated circuit system according to the first embodiment of theinvention,

FIG. 4 is a diagram showing a net list and a terminal table of thesemiconductor integrated circuit system according to the firstembodiment of the invention,

FIG. 5 is an explanatory view showing a connecting relationship of thesemiconductor integrated circuit system according to the firstembodiment of the invention,

FIG. 6 is a flowchart showing a design of a fan out according to thefirst embodiment of the invention,

FIG. 7 is an explanatory view showing the fan out according to the firstembodiment of the invention,

FIG. 8 is an explanatory view showing the fan out according to the firstembodiment of the invention,

FIG. 9 is an explanatory diagram showing a method of designing a packagesubstrate according to the first embodiment of the invention,

FIG. 10 is an explanatory diagram showing a method of designing aprinted wiring board according to the first embodiment of the invention,

FIG. 11 is an explanatory diagram showing the method of designing aprinted wiring board according to the first embodiment of the invention,

FIG. 12 is an explanatory view showing the method of designing a printedwiring board according to the first embodiment of the invention,

FIG. 13 is an explanatory view showing the designing method according tothe first embodiment of the invention,

FIG. 14 is an explanatory view showing the designing method according tothe first embodiment of the invention,

FIG. 15 is an explanatory view showing a designing method according to asecond embodiment of the invention,

FIG. 16 is an explanatory diagram showing the designing method accordingto the second embodiment of the invention,

FIG. 17 is an explanatory diagram showing the designing method accordingto the second embodiment of the invention,

FIG. 18 is an explanatory diagram showing the designing method accordingto the second embodiment of the invention,

FIG. 19 is an explanatory view showing a method of designing a packageaccording to the second embodiment of the invention,

FIG. 20 is a flowchart showing a method of designing a package accordingto a third embodiment of the invention,

FIG. 21 is an explanatory view showing the designing method according tothe third embodiment of the invention,

FIG. 22 is an explanatory view showing a method of designing a packageaccording to a fourth embodiment of the invention,

FIG. 23 is an explanatory view showing a method of designing a packageaccording to a fifth embodiment of the invention,

FIG. 24 is an explanatory view showing the method of designing a packageaccording to the fifth embodiment of the invention,

FIG. 25 is an explanatory view showing the method of designing a packageaccording to the fifth embodiment of the invention,

FIG. 26 is an explanatory view showing the method of designing a packageaccording to the fifth embodiment of the invention,

FIG. 27 is an explanatory view showing the method of designing a packageaccording to the fifth embodiment of the invention,

FIG. 28 is an explanatory view showing the method of designing a packageaccording to the fifth embodiment of the invention,

FIG. 29 is an explanatory view showing the method of designing a packageaccording to the fifth embodiment of the invention,

FIG. 30 is an explanatory view showing a method of designing a packageaccording to a sixth embodiment of the invention,

FIG. 31 is an explanatory view showing the method of designing a packageaccording to the sixth embodiment of the invention,

FIG. 32 is an explanatory view showing the method of designing a packageaccording to the sixth embodiment of the invention,

FIG. 33 is an explanatory view showing the method of designing a packageaccording to the sixth embodiment of the invention,

FIG. 34 is an explanatory view showing the method of designing a packageaccording to the sixth embodiment of the invention,

FIG. 35 is an explanatory view showing the method of designing a packageaccording to the sixth embodiment of the invention,

FIG. 36 is an explanatory sectional view showing the package accordingto the sixth embodiment of the invention,

FIG. 37 is an explanatory diagram showing a method of designing apackage according to a seventh embodiment of the invention,

FIG. 38 is an explanatory view showing the method of designing a packageaccording to the seventh embodiment of the invention,

FIG. 39 is an explanatory view showing the method of designing a packageaccording to the seventh embodiment of the invention,

FIG. 40 is an explanatory view showing a method of designing a packageaccording to an eighth embodiment of the invention,

FIG. 41 is an explanatory view showing a method of designing a packageaccording to a ninth embodiment of the invention,

FIG. 42 is an explanatory diagram showing a method of designing apackage according to a tenth embodiment of the invention,

FIG. 43 is an explanatory view showing the method of designing a packageaccording to the tenth embodiment of the invention,

FIG. 44 is an explanatory view showing a method of designing a packageaccording to an eleventh embodiment of the invention,

FIG. 45 is an explanatory view showing a method of designing a packageaccording to a twelfth embodiment of the invention,

FIG. 46 is an explanatory view showing a method of designing a packageaccording to a thirteenth embodiment of the invention,

FIG. 47 is an explanatory view showing a method of designing a packageaccording to a fourteenth embodiment of the invention,

FIG. 48 is an explanatory diagram showing a method of designing an LSIaccording to a fifteenth embodiment of the invention,

FIG. 49 is a diagram showing an apparatus for designing an LSI accordingto the fifteenth embodiment of the invention,

FIG. 50 is an explanatory diagram (a net list) showing a method ofdesigning an LSI according to the fifteenth embodiment of the invention,

FIG. 51 is an explanatory chart showing the method of designing an LSIaccording to the fifteenth embodiment of the invention,

FIG. 52 is a flowchart showing a method of designing an LSI according toa sixteenth embodiment of the invention,

FIG. 53 is an explanatory view showing the method of designing an LSIaccording to the sixteenth embodiment of the invention,

FIG. 54 is a flowchart showing a method of designing an LSI according toa seventeenth embodiment of the invention,

FIG. 55 is an explanatory view showing the method of designing an LSIaccording to the seventeenth embodiment of the invention,

FIG. 56 is a flowchart showing a method of designing a semiconductorintegrated circuit system according to a conventional example, and

FIG. 57 is an enlarged view showing a main part in FIG. 14.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments according to the invention will be described below in detailwith reference to the drawings.

The invention serves to implement a completely reverse design flow to aconventional design flow and to provide a semiconductor integratedcircuit system in which a mounting substrate such as a printed wiringboard is first designed, a package substrate mounting an LSI is designedbased on a result of the design of the mounting substrate and a layoutdesign of the LSI to be mounted on the package substrate is then carriedout to wholly optimize the printed wiring board, the package and the LSIwhich act as the mounting substrate, and countermeasures to be takenagainst an unnecessary radiation and a heat are excellent.

First Embodiment

Prior to explanation of the embodiments according to the invention,description will be first given to a concept of the invention.

FIG. 1 is an explanatory diagram showing a design flow and FIG. 2 showsan apparatus for designing a semiconductor integrated circuit system. Inthe embodiment, a system specification including, on a printed wiringboard, a semiconductor integrated circuit (LSI) to be accommodated in apackage and other electronic components such as a memory is investigated(system and specification investigation: Step 1001), the printed wiringboard is designed based on information about a component arrangement onthe printed wiring board (a design of the printed wiring board: Step1002). Then, a position of a ball to be an external connecting terminalon a package substrate constituting a package is investigated based onthe information about a component arrangement on the printed wiringboard and the package is designed in consideration of a signal wiring ofthe package (a design of the package: Step 1003). Thereafter, aninput/output arrangement of the LSI in which the signal wiring in thepackage is optimized is determined and an arrangement of an input/outputterminal 301 of the LSI is determined (a design of the LSI: Step 1004).

More specifically, the arrangement of the input/output terminal of theLSI is optimized based on information about the printed wiring board andthe package (the package substrate) in place of the internal conditionof the LSI so that the whole semiconductor integrated circuit systemcomprising the printed wiring board, the package and the LSI isoptimized.

Moreover, the optimum arrangement of a component and a wiring patternincluding the LSI on the printed wiring board and the signal wiring inthe package substrate constituting the package are also taken intoconsideration, and a problem such as an intersecting structure or anincrease in a wiring length is eliminated and an optimization is carriedout for an unnecessary radiation and heat for the whole system.Therefore, quality can be enhanced. Furthermore, a complicatedarrangement of the signal wiring is not generated. Therefore, it ispossible to reduce a man-hour, and furthermore, to correspond to anautomation.

Next, the embodiment will be described in detail. The embodiment isexecuted by setting a system/specification investigation, that is, acomponent arrangement result as input data. As shown in the blockdiagram of FIG. 2, the apparatus for designing a semiconductorintegrated circuit system to be used herein comprises a mountingsubstrate designing portion 150, a package substrate designing portion250 for designing the package substrate based on the design result, andfurthermore, a semiconductor integrated circuit designing portion 350for designing a semiconductor integrated circuit based on a designresult of the package substrate.

The mounting substrate designing portion 150 serves to design asemiconductor integrated circuit mounting substrate by setting a systemspecification as input data, and has such a structure as to comprise aregion dividing portion 151 and a wiring control portion 152 and tocarry out such a control as to investigate the specification of thesemiconductor integrated circuit system, to divide the mountingsubstrate into a plurality of regions through the region dividingportion 151, and to complete a wiring for each of the regions throughthe wiring control portion 152.

The region dividing portion 151 divides, into a plurality of regions, aregion including the semiconductor integrated circuit to be a designobject and a device designed previously therearound. Moreover, thewiring control portion 152 controls the wiring in such a manner that thewiring is completed in the regions obtained by the division of theregion dividing portion 151.

Moreover, the mounting substrate designing portion may be constituted touse, as input data, the system specification information which does notinclude the information about a design of a semiconductor integratedcircuit chip. Consequently, it is possible to design the mountingsubstrate with priority without taking the information about the designof a semiconductor integrated circuit chip into consideration.

Furthermore, the mounting substrate designing portion 150 includes adesigning portion for determining a virtual wiring leading point in aposition placed apart from an outer edge of the package substrate by apredetermined distance and carrying out a design to cause the wiringpattern to pass through the wiring leading point.

In the invention, moreover, it is desirable that the mounting substratedesigning portion 150 should include an intersecting control portion fordesigning the wiring leading point in such a manner that a lineconnecting an input/output pad of a semiconductor integrated circuit tobe a design target device, an internal connecting terminal (a bondingpoint of a bond finger) for a connection, to the input/output pad, ofthe package substrate to be connected to the input/output pad, anexternal connecting terminal of the package substrate to be connected tothe mounting substrate, and the wiring leading point does not have anintersecting region.

A ball grid array is used as the package, and there is used a packagesubstrate having a multilayer wiring structure including a four-layerconductor layer having a surface layer wiring, a power plane, a groundplane, and a lowermost layer wiring on which a ball constituting anexternal connecting terminal is formed. A conductor layer positioned ona surface layer mounting the LSI thereon includes a power ring and isconstituted to be connected to the power plane through the power ring insuch a manner that the wiring in the package substrate does not have theintersecting region.

The package substrate designing portion 250 serves to investigate a typeof the package to be applied and to design the package substrate inconsideration of a result of the design of the mounting substrate, aspecification of the system and a consumed power, and includes a powerplane dividing portion 251, a power control portion 252 and a divisioncontrol portion 253. The details will be described below. In theembodiment, the power plane is divided corresponding to a powerpotential, and furthermore, the region is also divided for each wiringlayer and a control is carried out to complete a wiring in the region,and the wiring is provided so as not to have the intersecting region.

The input data of the package substrate designing apparatus 250 includeat least the design result of the semiconductor integrated circuitmounting substrate designing portion 150. The dividing control portion253 of the package substrate designing apparatus 250 carries out adivision for each signal group and performs a control in such a mannerthat a wiring constituting a signal group corresponding to the componentis provided in the divided region depending on a position of a componentarrangement on the semiconductor integrated circuit mounting substrate.

Moreover, the power plane dividing portion 251 carries out a divisioninto a plurality of regions for each power unit in such a manner thatthe power plane constituting the package substrate corresponds to apower division on the mounting substrate.

Furthermore, the dividing control portion 253 carries out a design insuch a manner that the external connecting terminal of the packagesubstrate constitutes the ball grid array, the external connectingterminal forming surface is divided into eight regions and a signalwiring is completed for each region. Moreover, the grouping is carriedout corresponding to an array of the external connecting terminal, andthe design is carried out in such a manner that the signal wirings areadjacent to each other every group. Furthermore, the package substratedesigning portion may include a wiring control portion for carrying outa control in such a manner that the surface layer wiring and thelowermost layer wiring have a formation prohibiting region having apredetermined width from an end of the divided region, which is notshown.

Moreover, the semiconductor integrated circuit designing portion 350serves to carry out a circuit design including an input/output pad overthe design result of the mounting substrate and the design result of thepackage substrate in consideration of the internal condition andincludes a data input portion 351, an internal condition consideringportion 352, a pad arrangement correcting portion 353, an input/outputpad arranging portion 354 and an input/output cell designing portion355. The details will be described below, and the data input portion 351determines an input/output pad arrangement by setting the design resultof the semiconductor integrated circuit mounting substrate to be theinput data. Moreover, the internal condition considering portion 352carries out a correction in consideration of the internal condition ofthe LSI. The input/output pad arranging portion 354 designs thearrangement of the input/output pad of the semiconductor integratedcircuit corresponding to the arrangement of the external connectingterminal on the package substrate and the arrangement of the componenton the semiconductor integrated circuit mounting substrate. Theinput/output cell designing portion 355 determines a driving capabilityof an input/output cell to be connected to the input/output pad of thesemiconductor integrated circuit corresponding to the arrangement of thecomponent on the semiconductor integrated circuit mounting substrate.

FIG. 3 is a flowchart showing, in detail, the system/specificationinvestigating step 1001 to be executed prior to the printed wiring boarddesigning step 1002 in the steps illustrated in FIG. 1.

First of all, a consumed power of a component to be arranged on aprinted wiring board 100 such as an LSI or a memory is calculated fromthe system/specification (Step 1011). In that case, it is necessary toinvestigate any package to be used in relation to the LSI. For thisreason, the following investigation is executed.

Then, the number of power balls is estimated based on the consumed power(Step 1012). In that case, this is obtained by a calculation based on apower value which can be supplied per ball constituting the externalconnecting terminal of the package. The power value executes thecalculation for a power supply and a ground (GND) respectively.

Moreover, types of a signal and a power supply (grouping) and the numberare investigated based on a terminal table of a system and a signalconnection (a net list) as shown in FIGS. 4( a) to 4(c) and FIG. 5 onthe basis of the system specification (Step 1013).

At the Step 1013, the grouping of the signal and the power supply andthe number of power supplies belonging to the group are made clear,thereby estimating the necessary number of terminals (Step 1014).

Thus, the investigation is carried out based on the consumed power ofthe component to be arranged on the printed wiring board in the system.As a result, the investigation is made based on the necessary number ofpower balls which is calculated, the net list of the system and theterminal table to calculate the number of the balls.

The necessary number of the balls and a package corresponding to thenumber of the balls are determined from the two types of results ofinvestigations (Step 1015). For example, there is determined a use of apackage utilizing a package substrate having a three-layer structurewhich includes an external connecting terminal constituting a ball gridarray in which balls are arranged like a grid, for example.

When the package is determined, whether a fan out (leading) of eachwiring can be executed through the package is investigated (Step 1016).

Referring to a wiring rule of a printed-wiring assembly (a width of awiring, an interval, a size of a via or an interval) for a footprint ofa package (a shape of the package, an arrangement of a pin and thenumber of pins) and a structure of a substrate layer (the number ofsheets) in the case in which the printed wiring board is constituted bya multilayer substrate, the contents of the investigations to be carriedout are selected and whether a necessary wiring can be led is confirmed.

If it is decided that the necessary wiring cannot be led, then, theprocessing returns to the investigation of the package and areinvestigation (Step 1017) is executed.

If the necessary wiring can be led, the detailed design of the printedwiring board is started (Step 1018). (the processing proceeds to a nextphase).

According to the method, the design is first carried out from adownstream side toward an upstream side, that is, from the printedwiring board to the package substrate design and the LSI design when theprinted wiring board is to be designed in the design of thesemiconductor integrated circuit system, and the schematic position ofthe terminal array of the package is determined by setting, as inputdata, the information about the component arrangement result obtainedbased on the system specification information in the design of theprinted wiring board. Therefore, the restrictions of the package and theLSI are put with difficulties and it is possible to determine anarrangement of an input/output terminal or a layout of a wiring patternwhich is ideal for the printed wiring board. Consequently, the wiringrule and the substrate layer structure in the printed wiring board canbe investigated in a short turnaround time. In this connection, theinput/output terminals of the package and the LSI have already beendetermined in the conventional design. For this reason, it is necessaryto execute the design of the package again in order to carry out thereinvestigation. Depending on circumstances, there is a possibility thata change in the layout of the LSI might be required and a considerabletime and man-hour might be necessary.

In addition to the functions and advantages, according to the invention,it is possible to suppress an intersection of a wiring and an increasein a wiring length and to reduce a complicated arrangement of a signalwiring also in an increase in a scale and a speed and a change into amultibit of the semiconductor integrated circuit system. Accordingly, itis easy to automate the wiring.

(Fan Out)

Next, the fan out explained in the Step 1016 of FIG. 3 will be describedin detail.

At a conventional designing step, the fan out investigation is manuallyexecuted. In the embodiment, however, an automation is implemented.

First of all, as shown in the flowchart of FIG. 6, the fan out (Step1016) is carried out after the package determining step 1015. The inputand confirmation of necessary information is first executed.

Firstly, the input of package information about an LSI and a memorywhich are to be used is confirmed (Step 1161). The reason is that awiring leading method is varied depending on a shape of the package andthe number of pins (the number of terminals and the number of powersupplies).

Secondly, an input of information about a position of an arrangement onthe printed wiring board is confirmed (Step 1162). This is carried outto investigate which terminal (group) of a power supply and a signal ofthe LSI is subjected to the fan out in any direction depending on thearranging state of components provided around the LSI. Herein, a ball ona close side to a related component is assigned to a signal andconsideration is taken in order to prevent a wiring from being providedaround and a wiring length from being increased.

Thirdly, an input of information about a printed wiring board to be usedis confirmed (Step 1163). This is carried out because the number ofwirings which can be led is varied depending on specifications such as awiring rule of the printed wiring board and a structure of a substratelayer. It is possible to lead a larger number of wirings with smallerwiring width and pitch.

When the number of wiring layers is larger, moreover, more signal linescan be led. However, there are restrictions, for example, a cost isconsiderably increased and an actual manufacture is hard to perform. Inconsideration of these restrictions, it is necessary to determine a fanout position. For this reason, the input of these information isconfirmed.

Fourthly, a fan out point position FPL is determined as shown in FIG. 7(Step 1164). Herein, a necessary number of fan out points are set arounda package 200 to be disposed. The number is prepared corresponding tothe numbers of power supplies and signals of the package. A designeroptionally sets a distance from the package. In case of a memory 500,when the fan out points are not uniformly disposed on four sides but areintensively disposed on a close surface to the LSI, it is possible toprevent the wraparound of the signal.

Fifthly, a fan out order is determined (Step 1165) and the fan out pointis linked to a position of a ball to be an external connecting terminal.Herein, the setting of the fan out point is executed, and a wiring isthen executed from the ball of the package to a fan out point FP. Thewiring is led in order so as not to have an intersecting region (seeFIG. 8).

Thus, the position of the fan out point is determined, and the positionand the position of the ball are connected sequentially so that a wiringpattern having no intersection can be designed by itself.

When the fan out order is thus determined and the investigation of thefan out (Step 1016 in FIG. 3) is ended, and the investigation of thedesign and specification of a system is completed, the printed wiringboard is actually designed. Next, description will be given to a processfor designing an actual printed wiring board.

In the design of the printed wiring board, a flowchart in FIG. 9 isexecuted.

First of all, the investigation of a schematic specification of thewhole printed wiring board is executed. The detailed specification hasnot been determined yet. As the whole printed wiring board, therefore, aclarification is first executed for input and output data as shown inFIG. 10( a), and an input portion I and an output portion O aredetermined (an input/output determining step 1021). Moreover, anecessary schematic specification for a signal processing is determined.

As shown in FIG. 10( b), subsequently, a function data flow isinvestigated (Step 1022). More specifically, when the schematicspecification of input and output signals is determined at theinput/output determining step 1021, there is executed an investigationwhether the specification is satisfied with such a structure and orderor not. Then, a reduction is executed over each specificationconstituting the printed wiring board based on the schematicspecification.

As shown in FIG. 10( c), thereafter, the LSI and a main bus areinvestigated (Step 1023). In other words, a bus is formed from the inputportion I to the output portion O through an LSI 1, an LSI 2 and an LSI3 on the printed wiring board 100.

When respective specifications are fixed, furthermore, individualspecifications are implemented with structures of the components (LSI 1,LSI 2 and LSI 3) and how to exchange data is investigated. Moreover, atransfer is clarified for a flow of data to be a basis of a signalprocessing.

As shown in FIG. 10( d), subsequently, the division of a board and theinvestigation of a peripheral component are carried out (Step 1024).When the individual specifications and the data transfer are clarified,the division of the board is executed. There will be supposed the casein which the division is mainly carried out for each of processingcontents and a division into three parts is carried out through aboundary line D. The necessary LSI for the processing and necessarycomponents are investigated. Herein, the LSI 1, the LSI 2 and the LSI 3are connected and two memories M are connected to each of them.

Then, a dividing investigation is executed for each of the three partsobtained by the division through the boundary line D (Step 1025). Morespecifically, as shown in FIG. 11( a), an arrangement of the componentsfor each part obtained by the division is investigated, andparticularly, a region Sa in which an enhance design is regarded to benecessary is clarified.

As shown in FIG. 11( b), subsequently, a Codesign coverage is determined(Step 1026). For a portion such as a high speed interface (I/F) in whichthe Codesign is regarded to be required, an arrangement and a wiring areinvestigated, and a region is set within an optional range.

When the setting of the range is determined, thus, the processingproceeds to an investigating phase for a detailed specification as shownin FIGS. 11( c) and 11(d) (Step 1027).

The printed wiring board 100 is thus designed so that a wiring 101 isformed.

There will be considered the case in which a division into three regionsA, B and C is carried out through the boundary line D, and three powerplanes of VDDA, VDDB and VDDC are assigned as shown in FIG. 12. Aconnection is sequentially carried out from a position of a ball 202 onthe package substrate 200 toward the fan out point FP, and a wiringregion LA having no intersection is obtained as shown in an enlargedview illustrating a main part in FIG. 13. In this example, it isapparent that a wiring 101 which passes through the fan out point FPM ofthe memory from the ball position of the package of the memory M and isalmost parallel and regular from the semiconductor integrated circuitpackage fan out point FP to the ball position is formed.

As shown in FIGS. 14 and 57, moreover, as in the wiring 101 on theprinted wiring board around the semiconductor integrated circuit package200, the wiring 101 is arranged well without an intersection up to thefan out point FP in a cowiring region. When the fan out point isexceeded, however, an array state is changed. FIG. 57 is an enlargedview showing a main part in FIG. 14. For example, a wiring pattern on amounting substrate is led with a regularity from the position of theball 202 of the BGA package 200 mounting a semiconductor integratedcircuit (chip) 300 to a predetermined position. On the other hand, whenthe fan out point FP is exceeded, the regularity is changed. In otherwords, there is rarely a regularity. Herein, a line FPL connecting thefan out point FP takes a square shape.

The region subjected to the region division is connected to the powerplane for each region.

According to the structure, a wiring constituting a signal groupcorresponding to the component is arranged in the region divideddepending on the position in which the component is arranged on thesemiconductor integrated circuit mounting substrate. Therefore, a wiringlength can be reduced and a speed can be increased. Accordingly, thereis implemented a wiring design having no intersection which takes themounting substrate and the package substrate into consideration.Therefore, it is possible to provide a semiconductor integrated circuitsystem which can carry out a high speed driving operation and isexcellent in an unnecessary radiant characteristic and a heatcharacteristic.

Second Embodiment

Next, description will be given to a method of designing a packageaccording to a second embodiment of the invention.

For the package, there have been proposed various packages using a leadframe and a film carrier. Herein, there will be utilized a packagehaving a ball grid array structure using a multilayered structuresubstrate as a package substrate and using a ball as an externalconnecting terminal.

While the method of designing a printed wiring board to mount a packagesubstrate mounting a semiconductor integrated circuit chip has beendescribed in the first embodiment, description will be given to a methodof designing a package substrate to be used in the embodiment.

As shown in a schematic sectional view of FIG. 15, the package isconstituted by a package substrate 201 having a four-layer structureincluding a surface layer 201 a having a surface layer wiring, a powerlayer 201 b constituting a power plane, a ground layer 201 cconstituting a ground plane, and a lowermost layer 201 d having alowermost layer wiring constituting a ball pad for forming a ball. Ametal layer constituting the ground layer and the power layer in thepackage substrate 201 is formed by patterning a copper foil to have anoccupation area which is equal to or greater than 80% of a substratesurface. These four layers, that is, the surface layer, the power layer,the ground layer and the lowermost layer are laminated through aninsulating layer and are connected to respective terminals through aninner via H. A ball 202 is formed on the lowermost layer 201 d toconstitute an external connecting terminal and face mounting is carriedout over a wiring pattern of a printed wiring board (100).

The embodiment is characterized in that the result of the design of theprinted wiring board described in the first embodiment is used as inputdata to be used for designing a package substrate to mount an LSI chipwhen designing the package substrate, for example.

A flowchart for the method is shown in FIG. 16. First of all, a ballrange of the package substrate is designated corresponding to a floorplan of a printed wiring board from a result of the design of theprinted wiring board (Step 1601). In other words, for example, a formingrange of the ball 202 is determined corresponding to a presence range ofan inward end 302 of a wiring pattern 301 shown in FIG. 14.

Subsequently, a position of a signal line is determined from the floorplan of the printed wiring board corresponding to the forming range ofthe ball 202 on the package substrate (Step 1602).

Then, an array of a signal of the LSI is determined based on a ballarrangement (Step 1603).

According to the method, the signal arrangement of the package substrateis determined in consideration of the printed wiring board. Therefore,it is possible to implement a wiring which has no torsion and isexcellent in an electrical characteristic.

Depending on a position on the printed wiring board in which a componentis disposed, it is also possible to carry out grouping of the signal,thereby designing a package.

Next, FIG. 17 is a flowchart showing a method of determining an array ofa signal using the grouping of the signal in the package.

First of all, all signals to be used in an LSI—package printed wiringboard are input (Step 1701).

Subsequently, each component to be mounted on the printed wiring boardis temporarily arranged to create a floor plan (Step 1702).

Based on the arrangement of the component, grouping into several typesis carried out (Step 1703).

Then, the group is adapted to the floor plan of the printed wiring boardto designate a ball arrangement range of the package (Step 1704).

According to the method, the signal grouping is carried out depending onthe position on the printed wiring board in which the component isarranged. Therefore, it is possible to implement a wiring which has notorsion and is excellent in an electrical characteristic.

For example, in the package substrate 201 of the package shown in FIG.14, a ball arrangement region B_(A) is the ball arrangement range.

Next, description will be given to a method of executing the arrangementof the component in the package and a creation of a power planedepending on a power division. FIG. 18 is a flowchart and FIG. 19 is anexplanatory view showing the same.

First of all, each component of the printed wiring board 100 is arrangedto create a floor plan (Step 1801). Based on the floor plan, then, apower and ground plane region of the printed wiring board is set (Step1802).

Finally, a power and ground plane portion in which the printed wiringboard 100 and the package substrate 201 overlap each other istransferred onto the plane of the package substrate to form a structurein which a power plane 201 b is divided into three parts through aboundary line D as shown in FIG. 19 (Step 1803).

According to the structure, an easiness of a power design is enhanced.By the creation of the power plane depending on the power division,moreover, the easiness of the power design is enhanced. Furthermore, itis possible to reduce a power loss.

Thus, there is used the package substrate having the multilayerstructure comprising a plurality of conductor layers including the powerplane for each power unit in such a manner that the power planecorresponds to a region including the power plane on the mountingsubstrate. Therefore, a wiring can easily be carried out and a size canbe reduced.

The design is carried out in such a manner that the conductor layerconstituting the package substrate includes a power ring and a wiring inthe package substrate has no intersecting region through the power ring.Consequently, a degree of freedom of the wiring can be enhanced moregreatly and a parasitic capacitance can be reduced, and it is possibleto obtain a package which has a small size and can carry out a highspeed driving operation.

According to the method, moreover, the package substrate is designedafter the design of the printed wiring board. Therefore, it is possibleto carry out the design based on connecting information from asemiconductor integrated circuit to be a target to a peripheralcomponent of the semiconductor integrated circuit so as not to have anintersecting region.

By avoiding the intersecting region, thus, it is also possible to take acountermeasure against a heat radiation as well as a noise.

Third Embodiment

Next, description will be given to a third embodiment according to theinvention.

The method is characterized in that a plane of a package substrate isdivided into four regions and a signal wiring is completed for each ofthe regions in a design of the package substrate.

FIG. 20 is a flowchart showing a method of designing a package accordingto the embodiment, and particularly, a method of designing an in-regionwiring thereof. FIG. 21 is an explanatory view showing the designingmethod.

In the method, first of all, a size, a shape and a ball arrangement of aball (a ball grid array) to be an external connecting terminal of apackage substrate 200 and a size and a pad arrangement of an LSI 300 aresuperposed as input information, and superposition data are output asshown in FIG. 21( a) (Step 1021).

Then, a thickness and a length of a wire W and a bond finger BF are setto be input information in addition to the superposition data, and theball 202 and the pad of the LSI 300 are wired so as not to have anintersecting region, and design data subjected to the wiring as shown inFIG. 21( b) are output as output information (Step 1022).

Moreover, a region division is carried out by using, as the inputinformation, design data subjected to the wiring and region dividinginformation (Step 1023). As shown in FIG. 21( c), a division into fourparts is carried out along a diagonal line of the LSI. At the Step 1023,the design data subjected to the region division are output.

Furthermore, the design data subjected to the region division are usedas the input information and the wiring is executed to be completed inthe region as a wiring restriction (Step 1024). Thus, the wiring issequentially executed for each region. As shown in FIG. 21( d), thewiring for all of the regions is completed.

By carrying out the wiring through a division every region, thus, it ispossible to lessen data to interfere, thereby increasing a speed of aprocessing. Also in the case in which a correction is to be performedlater, it is sufficient that only the inner part of the region is takeninto consideration. Therefore, the correction processing can also becarried out easily.

While the region dividing step 1023 is executed after the connectingstep 1022 through the wire bond in the embodiment, the region dividingstep 1023 may be executed prior to the connecting step 1022 through thewire bond.

Fourth Embodiment

Next, description will be given to a fourth embodiment according to theinvention.

While the plane of the package substrate is divided into four regions inthe design of the package substrate and the signal wiring is completedfor each region in the embodiment, the fourth embodiment ischaracterized in that the plane is divided into eight regions.

As shown in FIGS. 22( a) and 22(b), a ball 202 is disposed on a packagesubstrate 201, and an LSI 300 is superposed thereon to form a squareregion on inner coordinates at an innermost periphery of a ball point,thereby creating an outermost circumferential frame LA1 of a wiringregion. An innermost circumferential frame LA2 to be an octagonal regionis created in order to surround a full bond finger BF. Then, a regionbetween the outermost circumferential frame LA1 and the innermostcircumferential frame LA2 is extracted by a logical operation and is setto be a wiring region WA. Thereafter, a region obtained by a divisionthrough a diagonal line is further divided into two parts and aone-eighth region is formed.

By the eight-division, it is possible to further simplify the wiring ascompared with the case of the four-division.

Fifth Embodiment

Next, description will be given to a fifth embodiment according to theinvention.

While the plane of the package substrate is divided into the four oreight regions in the design of the package substrate to complete thesignal wiring every region in the third and fourth embodiments,description will be given to a design of a wiring pattern for connectinga ball 202 to a bond finger BF in the fifth embodiment. A packagesubstrate 200 is constituted by four wiring layers including a surfacelayer wiring 201 a, a power plane 201 b, a ground plane 201 c and alowermost layer wiring 201 d in the same manner as shown in FIG. 15, anda protruded portion is formed on the lowermost layer wiring 201 d toconstitute a ball 202 to be an external connecting terminal. The surfacelayer wiring 201 a comprises a bond finger including a bond portionformed like a band along a peripheral edge of a semiconductor integratedcircuit and a finger portion extended to a position placed just abovethe external connecting terminal 202 to be connected from the bondportion, and a tip of the bond finger is connected to the correspondingexternal connecting terminal 202 through a via formed on the finger.

The bond finger is implemented by the surface layer wiring 201 a.

First of all, as shown in FIG. 23, the grouping of the ball 202 to bethe external connecting terminal formed on the package substrate iscarried out. The same group is formed every longitudinal line andnumbering is carried out.

Also in the bonding finger, then, the numbering is carried out for eachgroup element number of the ball 202. Since the ball has three lines,the bond finger is arranged to have elements every three lines, forexample, C1, 2, 3, D1, 2, 3 . . . except for A1, B1 and B2 on an end.

As shown in FIG. 24, thereafter, a wiring cell prepared for each groupis disposed. In other words, corresponding wiring cells Ce1 and Ce2 areprepared for a corner portion and a repeating portion. Two types areprepared every one-eighth division. However, corresponding wiring cellsCe3 and Ce4 which are inverted transversely on each side are prepared sothat four types of wiring cells in total are prepared.

Thus, the wiring cells Ce1, Ce2, Ce3 and Ce4 are arranged and a point onwhich a lead wire from the bond finger intersects an innermostcircumferential frame LA2 is set to be a bond finger leading point, anda lead wire is provided in such a manner that an interval is uniform ona segment A as shown in FIG. 25.

As shown in FIG. 26, then, a ball leading point and a leading point fromthe bond finger, that is, the innermost circumferential frame LA2 and anoutermost circumferential frame LA1 are wired. The wiring is startedfrom the corner portion and a processing is carried out for each group.The wiring is executed like a grid with a wiring direction maintainedfrom a wiring end of a group in which the leading has already beencompleted to an end in a wiring enable region. An oblique direction isset to be main. If impossible, the wiring is executed in an upwarddirection or a transverse direction.

Thus, the wiring is sequentially carried out as shown in FIG. 27 and thewiring is completed as shown in FIG. 28.

For the balls in three lines, three wirings are required. As shown inFIGS. 29( a) and 29(b), it is possible to use the ball 202 which isaligned on a center with respect to a wiring 203 and the ball 202 whichis aligned on a right side.

As a variant, in the case in which a direct wiring from the ball lead tothe bond finger is carried out, the wiring is obtained as shown in FIG.29.

According to the method, the grouping is carried out for each terminalto be connected in a divided region, corresponding terminals in thegroup are wired between the ball leading point and the leading pointfrom the bond finger, that is, the innermost circumferential frame LA2and the outermost circumferential frame LA1. Consequently, it ispossible to easily implement a uniform wiring having no intersection.Thus, it is possible to form a package substrate which is excellent inan unnecessary radiant characteristic and a heat characteristic.

Sixth Embodiment

Next, description will be given to a sixth embodiment according to theinvention.

In the fifth embodiment, the description has been given to the design ofthe wiring pattern of the surface layer wiring for the connection of theball 202 to the bond finger BF in the design of the package substrate.In the sixth embodiment, with reference to FIGS. 30 to 35, descriptionwill be given to a design of a wiring pattern in which a bond finger isconstituted in two lines, a surface layer wiring from the bond finger onan inside to a via is formed and a connection to the ball 202 is carriedout through a lowermost layer wiring. FIG. 36 is a sectional explanatoryview.

First of all, as shown in FIG. 30, the grouping of the ball 202 to be anexternal connecting terminal formed on the package substrate is carriedout. Numbering is carried out to set the same group every ball in threelines positioned on an inside of three lines of an outermost layer.

The bond finger is also disposed on the inside of A1, B1, B2, C1, 2, 3,D1, 2 and 3 shown in FIG. 23. The numbering is carried out each numberof group elements of the ball 202 in each row. Since the balls aredisposed in three columns, the bond finger is disposed in order to haveelements every three columns in each row like c1 c2, c3, d1, d2, d3 . .. except for a1, b1 and b2 on an end.

As shown in FIG. 31, then, wiring cells prepared for each group arearranged. In other words, corresponding wiring cells Ce01 and Ce02 areprepared in a corner portion and a repeating portion. Although there aretwo types every division into eight parts, corresponding wiring cellsC0e3 and Ce04 having sides inverted transversely are prepared and fourtypes of wiring cells in total are prepared.

As shown in FIG. 32, thus, the wiring cells Ce01, Ce02, Ce03 and Ce04are arranged to form a surface layer wiring from the bond finger to thevia. Herein, the wiring is carried out toward a right side to create thevia. At this time, a minimum rule is applied to the wiring and a viapitch. The via is arranged in an upward direction, and an X-coordinatedirection is shifted to a negative direction when the arrangement cannotbe carried out. Thus, the arrangement in the upward direction from belowis repeated.

Consequently, the surface layer wiring and the via are generated asshown in FIG. 33.

A lowermost layer wiring is drawn to trace the surface layer wiring fromthe created via, and is led to a portion placed just below the bondfinger as shown in FIG. 34.

Finally, the ball lead and the via lead are sequentially connectedthrough a grid wiring so that a wiring shown in FIG. 35 is completed.

FIG. 36 shows an A-A section.

Thus, it is possible to efficiently form a package substrate having ahigh reliability also in an increase in the number of terminals.

Seventh Embodiment

Next, description will be given to a seventh embodiment according to theinvention.

In the embodiment, description will be given to a net assignment inmounting of a wire bonding type. FIG. 37 is a flowchart and FIG. 38shows a relationship between a package substrate 200 and an LSI 300.

Description will be given to a region division in which the packagesubstrate 200 is divided into eight regions as shown in FIG. 38.

In the embodiment, as shown in FIG. 37( b), a designing apparatus 20 ispreviously provided with an automatic dividing portion (Routing keein)21 for dividing a surface of a package substrate, a loop checkingportion 22 for confirming whether a wiring for a connection of aninput/output pad of an LSI to a ball is closed in a region, anintersection confirming portion 23 for confirming whether a wiring for aconnection of the input/output pad of the LSI to the ball intersectseach other in the region or not (a checking function in an arrangementof a bond finger and a wire), an automatic wiring portion 24 having anautomatic wiring function, and a via arrangement limiting portion 25having a function such as a via arrangement limiting function, and it ispossible to easily carry out an automatic design at a high speed with ahigh precision.

First of all, a size, a shape and a ball arrangement of a ball 202 of aBGA in the package substrate 200, and a size of the LSI 300 and anarrangement of an I/O pad 302 are set to be input information, andrelated data of the BGA and LSI, that is, data obtained by superposingthem are obtained (Step 3701).

The data are input as design data and region dividing information isobtained as output information in the automatic dividing portion 21(Step 3702). Herein, it is checked whether the wiring is closed on aboundary of the region division in the loop checking portion 22 or not.If the wiring is not closed, the arrangement of the ball 202 and the I/Opad 302 is shifted.

By using the region dividing information, column grouping of the balland the I/O pad is carried out by setting column grouping information asinput information. Thus, design data subjected to the region divisionand the column grouping are obtained (Step 3703).

By using the region dividing information, the column grouping for theball and the I/O pad is carried out by setting the column groupinginformation and I/O pad order defining information to be inputinformation. Consequently, there are obtained design data subjected tothe region division, the column grouping and order formation (Step3704).

Furthermore, information for which the region division in a dividedregion, the column grouping and the I/O pad order are determined is setto be input information, and the ball and the input/output pad order arerelated for each column group in the divided region to carry out aconnection through a bond finger BF. Then, the intersection confirmingportion 23 confirms whether a wiring intersection is present or not.Although the same numbers are connected, I/O pads connected to a powerring 205 and a ground ring 206 are excluded. The power ring 205 and theground ring 206 are directly subjected to wire bonding from power padsPP and PG. Thus, a net is propagated from a component having the net toa component having no net (a net assignment step 3705). The automaticwiring is carried out by using the automatic wiring portion 24 and thevia arrangement limiting portion having the function of limiting thearrangement of a via. If one column is impossible for the bond finger ona rule basis, the number of stages is increased to carry out anautomatic processing. In the automatic processing, a control is carriedout based on an arrangement rule of the bond finger and that of the wireand a uniform arrangement is thus performed.

Consequently, it is possible to carry out a propagation to an optimumterminal in order to obtain information about a printed wiring board.

The wiring is carried out on a surface layer in principle. In the casein which the arrangement is hard to perform by only the surface layer,the wiring is carried out on the lowermost layer, that is, the ballforming layer as described above (see FIG. 32).

This example is shown in FIG. 39. In the example of FIG. 39, a bondfinger BF1 positioned on an inside of the package substrate is connectedto an I/O pad P1 on an outside of the LSI 300, and furthermore, a bondfinger BF2 positioned on an outside of the package substrate isconnected to an I/O pad P2 on an inside of the LSI 300.

In the embodiment, moreover, a wiring forming region, that is, a regionRKI in which the wiring is to be carried out is determined inconsideration of a wiring role, and a wiring prohibiting region isformed in a region provided apart from a boundary line D of the regionat a predetermined interval a. There is a region in which the via is notformed in a width of 2 a obtained by adding the interval a betweenadjacent regions (Via keepin) in which vias are formed to the intervala. Consequently, a width of a power plane is maintained. When the via isformed, the power plane is removed around the region so that an area ofthe power plane is reduced and a current path becomes narrow ordisconnected. By maintaining the region in which the via is not formed,thus, it is possible to ensure the current path. In other words, thecurrent path in the power plane is maintained in a predetermined widthand the power plane is effectively ensured, and furthermore, the powerplane can be prevented from being a floating region.

Moreover, the automatic dividing portion (Routing keein) 21, the loopchecking portion 22, the intersection confirming portion 23, theautomatic wiring portion 24 and the via arrangement limiting portion 25are previously provided in the designing apparatus 20. Therefore, anautomatic wiring can be carried out very easily and it is possible toform a package substrate which is excellent in an unnecessary radiatingcharacteristic and a heat characteristic.

Eighth Embodiment

Next, description will be given to an eighth embodiment according to theinvention.

In the embodiment, description will be given to a net assignment inmounting of a flip chip type. FIG. 40 shows a relationship between apackage substrate 200 and an LSI 300F of the flip chip type.

Description will be given to the package substrate 200 divided intoeight regions as shown in FIG. 40. The package substrate 200 has afour-layer structure including a surface layer wiring including a pad BPto be directly connected to the LSI 300F, a power plane, a ground planeand a lowermost layer wiring forming a ball 202.

FIG. 40 shows an arrangement of pads PP and PG of the LSI to beconnected to the power plane and the ground plane of the packagesubstrate 200, and pads PS 1 . . . PS 7 . . . for a connection to asignal line. The surface layer wiring of the package substrate 200 isalso provided with a bonding pad BP corresponding to the pads PP and PGof the LSI and pads PS 1 . . . PS 7 . . . .

As shown in an arrow S1, balls 202-4, 5 and 6 on an inside are providedwith a wiring pattern by using the surface layer wiring from the padsPSs 4, 5 and 6.

As shown in an arrow S2, moreover, balls 202-1, 2 and 7 on an outsideare provided with a wiring pattern by using the lowermost layer wiringthrough a via (not shown) from the pads PSs 1, 2 and 7.

Since an actual design is carried out in the same manner as in theembodiments, description will be omitted. In an automatic wiring, thewiring is carried out on the surface layer and the lowermost layer inprinciple. The outside pad is subjected to a lowermost layer wiringthrough a via, and the inside pad is subjected to a surface layerwiring.

Thus, it is also possible to apply the invention to a package substrateof a flip chip type in addition to a package substrate of a wire bondingtype.

Ninth Embodiment

Next, description will be given to a ninth embodiment according to theinvention.

In the embodiment, description will be given to a net assignment inmounting of a flip chip type in the same manner as in the eighthembodiment as shown in FIG. 41. However, the embodiment is differentfrom the package substrate 200 shown in FIG. 40 in that an LSI 300F of aflip chip type is small and a ball is not disposed under the LSI 300F.

Description will be given to a package substrate 200 which is dividedinto eight regions as shown in FIG. 41. The package substrate 200 alsohas a four-layer structure including a surface layer wiring having a padBP to be directly connected to the LSI 300F, a power plane, a groundplane and a lowermost layer wiring for forming a ball 202.

FIG. 41 shows an arrangement of pads PP and PG of the LSI which are tobe connected to the power plane and the ground plane of the package.substrate 200, and pads PS 1 . . . PS 7 . . . for a connection to asignal line. The bonding pad BP is also formed on the surface layerwiring of the package substrate 200 corresponding to the pads PP and PGof the LSI and the pads PS 1 . . . PS 7 . . . .

As shown in an arrow S3, a wiring pattern is formed on balls 202-3, 4, 7and 8 in two lines on an inside by using a surface layer wiring on thepads PSs 3, 4, 7 and 8 on an inside.

As shown in an arrow S4, moreover, a wiring pattern is formed by using alowermost layer wiring through a via (not shown) from outside pads PSs1, 2, 5, 6, 9 and 10 on an outside.

An actual design is carried out in the same manner as in theembodiments. Therefore, description will be omitted. In an automaticwiring, the wiring is performed on a surface layer and a lowermost layerin principle, and the lowermost layer wiring is carried out over the padon the outside through a via and the surface layer wiring is carried outover the pad on the inside.

Also in the embodiments, thus, the package substrate is designed in sucha manner that an external connecting terminal of the package substrateconstituting a ball grid array divides a plane of the package substrateinto eight regions and a signal wiring is completed for each of theregions. Therefore, it is possible to easily carry out a wiring with ahigh workability.

Tenth Embodiment

Next, description will be given to a tenth embodiment according to theinvention.

In the embodiment, description will be given to grouping of a signal ina design of a package substrate and a swap of the signal as shown inFIG. 42.

First of all, a BGA and an LSI to be external connecting terminals arearranged (S4201), and a schematic design for wire bonding (S4202), aregion division (S4203), signal grouping (S4204) and an in-region wiring(S4204) are carried out.

In the grouping, three trains of bond fingers and three vertical trainsof balls are grouped as shown in FIGS. 23 to 28 in the fifth embodiment.

Then, the swap of the signal is carried out if necessary (S4205).

More specifically, there is employed a structure in which bondingportions of the bond fingers are arranged adjacently to the verticaltrain of the BGAs.

By changing the arrangement of three bonding portions in these groups ina correction as described above, consequently, it is possible to easilycarry out the correction.

In other words, in the case in which bond fingers BFs 1, 2 and 3 formedby the surface layer wiring of the package substrate and balls 202-1, 2and 3 formed by the lowermost layer wiring of the package substrate aresequentially connected to each other as shown in FIG. 43( a), it ispossible to carry out the correction to connect the bond fingers BFs 1,2 and 3 to the balls 202-3, 1 and 2 formed by the lowermost layer wiringof the package substrate by only changing a wiring corresponding to thefinger as shown in FIG. 43( b).

In the case in which the bond fingers BFs 1, 2 and 3 formed by thesurface layer wiring of the package substrate and the balls 202-1, 2 and3 formed by the lowermost layer wiring of the package substrate aresequentially connected to each other as shown in FIG. 43( a), moreover,it is possible to carry out the correction in order to connect the bondfingers BFs 1, 2 and 3 and the balls 202-3, 2 and 1 formed by thelowermost layer wiring of the package substrate to each other by onlychanging the wiring corresponding to the finger so as to be inverted asshown in FIG. 43( c).

Thus, it is possible to easily carry out a correction and a change byperforming grouping for each bond finger having three fingers.Accordingly, an automatic wiring can also be carried out easily. In thecase in which a connection between the groups is to be executed, acountermeasure can also be taken by utilizing another layer to carry outthe wiring or swapping an input/output terminal of the LSI.

More specifically, in a package substrate of a BGA type, a lowermostlayer wiring constitutes a ball to be an external connecting terminal,and a surface layer wiring is provided with a bond finger including abond portion formed like a band along a peripheral edge of thesemiconductor integrated circuit and a finger portion extended to aposition placed just above the external connecting terminal to beconnected from the bond portion. A tip of the bond finger is connectedto a corresponding external connecting terminal through a via and threetips are grouped. By regulating the arrangement of the finger for thebond portion, consequently, it is possible to swap an output terminalwell.

Eleventh Embodiment

Next, description will be given to an eleventh embodiment according tothe invention.

In the embodiment, description will be given to a swap of a signal inthe case in which grouping is carried out every four signals as shown inFIG. 44.

In the embodiment, in the case in which bond fingers BFs 1, 2, 3 and 4formed by a surface layer wiring of a package substrate and balls 202-1,2, 3 and 4 formed by a lowermost layer wiring of the package substrateare sequentially connected to each other as shown in FIG. 44( a), it ispossible to carry out a correction to connect the bond fingers BFs 1, 2,3 and 4 to the balls 202-3, 1, 2 and 4 formed by the lowermost layerwiring of the package substrate by only changing a wiring correspondingto the finger as shown in FIG. 44( b).

In the case in which the bond fingers BFs 1, 2, 3 and 4 formed by thesurface layer wiring of the package substrate and the balls 202-1, 2, 3and 4 formed by the lowermost layer wiring of the package substrate aresequentially connected to each other as shown in FIG. 44( a), moreover,it is also possible to carry out a correction to connect the bondfingers BFs 1, 2, 3 and 4 and the balls 202-3, 1, 2 and 4 formed by thelowermost layer wiring of the package substrate by only changing thewiring corresponding to the finger so as to invert three fingers in thesame manner as in the tenth embodiment as shown in FIG. 44( c).

FIGS. 44( d) to 44(f) are the same.

Thus, it is possible to easily carry out the correction and change byperforming grouping for each bond finger having four fingers.Accordingly, an automatic wiring can also be carried out easily. In thecase in which the connection between the groups is executed, it ispreferable to utilize another layer to carry out a wiring or to swap aninput/output terminal of an LSI.

Twelfth Embodiment

Next, description will be given to a twelfth embodiment according to theinvention.

In the embodiment, as shown in FIGS. 45( a) to 45(c), there is employeda structure in which bond fingers BFs 11, 12 and 13 on an inside arecompleted with a lowermost layer wiring to be the same layer as a balland are connected to three trains of balls by using a surface layerwiring.

Since the embodiment is the same as the embodiments 10 and 11 inprinciple, description will be omitted. By carrying out grouping with arelationship of three trains of bond fingers and three vertical trainsof balls, it is possible to carry out a physical connection even if anet is swapped in each group.

More specifically, according to the structure, a signal group is dividedcorresponding to an arrangement of an external connecting terminal (aball) and a bonding pad of a bond finger and input/output terminals of asemiconductor integrated circuit chip to be connected thereto for eachgroup are arranged. Therefore, it is possible to easily carry out a swapby only changing an extending destination of the finger.

Thirteenth Embodiment

Next, description will be given to a thirteenth embodiment according tothe invention.

In the embodiment, as shown in FIGS. 46( a) to 46(c), there is employeda structure in which bond fingers BFs 11, 12, 13 and 14 on an inside arecompleted with a lowermost layer wiring to be the same layer as a balland are connected to four trains of balls by using a surface layerwiring.

By carrying out grouping with a relationship of four trains of bondfingers which are transversely adjacent to each other and four verticaladjacent trains of balls, it is possible to carry out a physicalconnection even if a net is swapped in each group.

According to the structure, a lowermost layer wiring is used so that adegree of freedom of a wiring can be increased and a swap can easily becarried out.

Fourteenth Embodiment

Next, description will be given to a fourteenth embodiment according tothe invention.

In the embodiment, description will be given to a swap on an outside ofa group with reference to FIGS. 47( a) to 47(c).

Referring to a bond finger BF and a ball 202, if the bond finger BFwhich is adjacent in a transverse direction and a vertical train ofballs are grouped and a wiring region 211 for each group can be definedas shown, it is possible to previously investigate the swap of the ball.

As shown in FIGS. 47( a) and 47(b), a connecting destination routeregulating region 210 is disposed so that a wiring can be bent and aswap between the groups can be carried out.

Moreover, it is hard to carry out a net exchange on the outside of thegroup as shown in FIG. 47( c).

By using a part of a power plane, furthermore, it is possible to carryout the swap.

In case of a bond finger on an inside, moreover, it is possible toutilize a surface layer wiring and a lowermost layer wiring. In somecases, therefore, the swap can be carried out.

Fifteenth Embodiment

Next, description will be given to a fifteenth embodiment according tothe invention.

A design of an LSI will be described below.

In the embodiment, in the design of the LSI, there are provided a stepof determining an input/output pad arrangement by setting, as inputdata, a result of a design obtained at a step of designing asemiconductor integrated circuit mounting substrate, a step of thencarrying out a modification in consideration of an internal condition ofthe LSI, and a correcting step of correcting the input/output padarrangement by setting, as input data, an output at the step of carryingout a modification.

FIG. 48 is a flowchart showing a method of designing the LSI.

Herein, input data are PCB driven designed data. At a “PCB parasiticelement extracting step” S4800, the PCB design data are set as inputinformation to extract parasitic passive elements such as inductance L,resistance R, capacitance C and mutual inductance K of a PCB wiring anda component such as a discrete or a memory.

At a “PKG parasitic element extracting step” S4801, package (PKG) designdata are set as an input to extract a PKG wiring and LRCK of a bondingwire (in case of a wire bonding type).

At an “LSI parasitic element extracting step” S4802, then, an IO cell, apad, a decoupling capacitive cell are extracted and LRCK of a powernetwork for supplying a power to the IO cell is extracted.

At an “integrated net list generating step” S4803, furthermore,information extracted at the PCB/PKG/LSI parasitic element extractingstep is set as an input to connect the PCB and the PKG, and the PKG andthe LSI to each other. At the same time, terminal setting, an inputsignal waveform and a signal measuring point for an enable signal of theIO cell are specified. The signal measuring point specifies to measurean output terminal of the IO cell, a BALL of the PKG and a signalwaveform in a component on the PCB. The connected and set informationare created in an SPICE net list format. Moreover, the IO cell may takea case of designation with an SPICE subcircuit or a designating methodwith an input/output buffer information specification (IBIS).

At a “circuit simulation step” S4804, a circuit simulation is carriedout by using a circuit simulator such as an HSPICE or an SPECTRE and asignal waveform is measured.

At a “signal quality deciding step” S4805, referring to a waveform onthe signal measuring point, a voltage level, a skew between signals, anover/undershoot height, and a ringing width are then calculated and itis decided whether predetermined specifications are satisfiedrespectively or not. If the specifications are not satisfied, settingfor changing a driving capability of the IO cell is added to the netlist created in the “integrated net list generating step” S4803 at a“driving capability changing step” S4806, and the processing returns tothe “circuit simulation step” S4804 again.

As described above, in case of the PCB driven design, a wiring and acomponent on the outside of the LSI are determined in the LSI designingstage. Therefore, it is possible to determine a driving capability ofthe IO cell of the LSI correspondingly. As a result, the quality of asignal of the LSI, the PKG and the PCB can wholly satisfy thespecifications in the designing stage. Consequently, it is possible toenhance quality and to reduce a future correction man-hour.

The flowchart is executed by using an analyzing apparatus shown in FIG.49. The analyzing apparatus comprises equivalent impedance informationestimating means 13 for calculating and estimating equivalent impedanceinformation based on semiconductor integrated circuit mounting substrate(PCB) information 10, circuit information 11 of the LSI, and packageinformation 12 of the LSI chip, and analyzing means 15 for calculatingand analyzing an unnecessary radiant noise and a heat characteristicbased on equivalent impedance information 14, and serves to output ananalysis result 16. There is provided optimizing means 17 for optimizingan unnecessary radiant noise and a heat characteristic based on theequivalent impedance information 14 obtained by the equivalent impedanceinformation estimating means 13, and an optimization is carried out bythe optimizing means 17 and a layout design is carried out based on anoptimization result 18 which is obtained.

The equivalent impedance information estimating means 13 is constitutedto extract LRCK of a PCB wiring and a component such as a discrete or amemory, and furthermore, to extract a chip area from the circuitinformation 11 which is extracted, a position of a power pad, a width, alength and a material of a power wiring from power information, and atype of a package from package information. From these information, itis possible to obtain R, L and C information shown in FIG. 50.

The analyzing apparatus can be executed based on the circuit informationin a floor plan stage.

Next, description will be given to a method for executing an unnecessaryradiation and a thermal analysis by using the analyzing apparatus,thereby generating an integrated net list.

First of all, a functional design is carried out and a logical design isthen performed in the floor plan stage. In that stage, a chip area isdetermined and a width, a length and a material of a power wiring areobtained from power information, and furthermore, a position of a powerpad is obtained from the package information 12 as shown in FIG. 49, anda resistance R, a capacity C and an inductance L of a connecting portionare estimated to obtain an equivalent impedance from these values in theequivalent impedance estimating means 13 as shown in FIG. 50.

When the chip area is determined, the resistance R is decided. When acomponent arrangement on the semiconductor integrated circuit mountingsubstrate, a package and a position of the power pad are determined, alength of a lead is decided so that an inductance is determined. For amethod of estimating the resistance or the inductance, various methodshave been proposed. By simply multiplying a chip area with acoefficient, however, it is possible to calculate an approximateresistance value.

Since an approximate area of a power supply is determined from the chiparea, a capacity between the power supplies is estimated. When the chiparea is determined, moreover, the number of transistors is estimated sothat a gate capacity is also estimated. When an occupation area of thetransistor is estimated from the chip area and the number of thetransistors, a wiring capacity is estimated.

Thus, an equivalent impedance is estimated. Therefore, it is possible toreduce an amount of a calculation. Thus, it is possible to execute ananalysis at a high speed with a high precision and reliability.

Based on the analysis result 16 thus obtained, an EMI noise and a heatcharacteristic are optimized by the optimizing means 17. Thus, optimumRCL information is obtained.

Thus, the integrated net list shown in FIG. 50 is generated and thecircuit simulation is carried out based thereon (S4804).

Subsequent steps have been described above.

At the “signal quality deciding step” S4805, it is decided whether apredetermined specification is satisfied for a signal waveform thuscalculated or not. In the case in which a waveform is obtained on thesignal measuring point as shown in FIGS. 51( a) and 51(b), it is decidedwhether a predetermined specification is satisfied for a voltage level,a skew between signals, an over/undershoot height, and a ringing widthor not. As an example of the specification, an overshoot height t1 isset to be equal to or smaller than 50 mV, the ringing width is set to be0 or be equal to or smaller than 50 mV around VDD, the voltage level isset to be 0.8 VDD to VDD, and a skew t4 is set to be 100 ps. In the casein which these specifications are not satisfied, setting of a change inthe driving capability of the IO cell is added to the net list createdat the “integrated net list generating step” S4803, and the processingreturns to the “circuit simulation step” S4804.

Sixteenth Embodiment

Next, description will be given to a sixteenth embodiment according tothe invention.

Description will also be given to a design of an LSI. FIG. 52 is aflowchart showing a designing method and FIG. 53 is an explanatory viewshowing the same.

The embodiment is characterized in that a PKG and the LSI are designedbased on an ideal PCB specification and an ideal set (=PCB+PKG+LSI) iscompleted in total. However, in the case in which a memory IF isactually given as a hard macro in the LSI, for example, there is arestriction that a terminal position of the memory interface (IF) cannotbe changed. For this reason, it is necessary to previously take thecircumstances of an LSI 300 into consideration in the investigation ofthe specification of a PCB 100 because it is supposed to meet with greatdifficulties, for example, a wiring between memories M1/M2 on the memoryinterface (IF) and the PCB cannot be carried out in the future.Accordingly, the flowchart for the processing shows a flow fordetermining the PCB specification which can be actually implementedwhile aiming at the ideal PCB specification.

At a “system and specification investigating step” S5200, specificationsof a product, for example, a function and a memory capacity aredetermined. At a “first PCB specification determining step” S5201, anideal PCB specification capable of implementing the specificationdetermined at the “system and specification investigating step” S5200 isdetermined. The ideal PCB specification implies a specification in whicha component can be arranged and a wiring can be provided in such amanner that a PCB area and the number of layers can be minimized. In theideal PCB specification, moreover, a noise sensitive component is notdisposed close to a noise generating source in consideration of anelectric/noise characteristic.

At an “LSI specification extracting step” S5202, next, a restriction tobe observed in an LSI designing stage is extracted.

In the case in which there is a memory IF which cannot be included inone side of the LSI, and furthermore, the memory IF is present as a hardmacro as shown in FIG. 53( b), a wiring can be provided more easily withan arrangement in a position making a pair with the memory IF as shownin FIG. 53( c) than an arrangement of memories M1/M2 shown in FIG. 53(a) in order to implement the memories M1/M2 on a PCB and a wiring of thememory IF. In case of the arrangement shown in FIG. 53( a), componentsother than the memory are arranged in the vicinity of an upper side ofthe LSI 300. Consequently, it is supposed that a wiring for thesecomponents is also hard in addition to the wiring of the memory.Accordingly, it is necessary to investigate the PCB specification takingthe LSI specification into consideration.

At a “second PCB specification determining step” S5203, a PCBspecification output at the “first PCB specification determining step”S5201 is added to a specification extracted at the “LSI specificationextracting step” S5202 to carry out a change into an ideal PCBspecification as shown in FIG. 53( c). In the PCB specification, the LSIspecification is also taken into consideration. By carrying out a designin order of. PCB→PKG→LSI, therefore, it is possible to carry out adesign which can satisfy everything.

As described above, in a PCB driven design, there is a high possibilitythat an impossibility might be generated in the LSI design if thespecifications of the PKG and the LSI are disregarded and an ideal PCBspecification is pursued. In the PCB specification design, thespecification is determined in consideration of a restriction which isto be absolutely observed in the LSI. Consequently, it is possible toimplement a design satisfying the respective specifications in order ofPCB→PKG→LSI at a time.

Seventeenth Embodiment

Next, description will be given to a seventeenth embodiment according tothe invention.

Description will be given to a design of an LSI using package PKGinformation.

In the embodiment, there are provided a step of determining aninput/output pad arrangement by setting package information as inputdata in the design of the LSI, a step of then carrying out amodification in consideration of an internal condition of the LSI, and astep of correcting the input/output pad arrangement to carry out anoptimization by setting, as input data, an output at the step ofcarrying out a modification.

As shown in a flowchart of FIG. 54 and an explanatory view of FIG. 55,in the embodiment, an IO position of an LSI is optimized by using PKGinformation.

The embodiment is constituted by a step S5401 of inputting packageinformation such as a ball position of a package 200 and a net nameassigned to a ball, a step S5402 of inputting a net list and a physicallibrary of a cell, a step S5403 of specifying a chip size of an LSI 300,a step S5404 of arranging an Driver cell in consideration of a ballposition of a package, a step S5405 of inserting a power cell inconsideration of a position of an IODriver cell arranged at the stepdescribed above, and a step S5406 of arranging a PAD in such a mannerthat a chip size is reduced after the IODriver cell and the power cellare arranged.

FIG. 55( a) shows package information used in the embodiment. In thedrawing, a net has already been assigned to a ball 202 in accordancewith a restriction imposed from a PCB 100 side. Next, information on theLSI side (the net list and the physical library) are input and a size ofthe LSI to be a target is set as shown in FIG. 55( b). At this time, the10Driver is not arranged. However, coupled information on the package200 side and the LSI 300 side are built as the net list information.

Next, the IODriver cell is arranged in accordance with the net assignedto the ball 202 of the package 200 in FIG. 55( c). As a method ofarranging the IODriver, a net length from the ball 202 to the IODrivercell is minimized and the respective nets are prevented from crossingeach other.

Next, a necessary power cell for the arranged IODriver is inserted inFIG. 55( d). In FIG. 55( e), then, a PAD cell is given to the IODrivercell and the power cell which are arranged.

By using the method, the arrangement of the IODriver and the PAD cell isobtained in accordance with a restriction imposed on the package side.Therefore, it is possible to obtain a package wiring having an excellentelectrical characteristic with a torsion. As described above, moreover,the ball position of the package is determined in accordance with therestriction on the PCB side. By arranging the IODriver and a PAD cell306 in accordance with the restriction on the package side, therefore,it is possible to carry out an IODriver cell and PAD cell arrangement onthe LSI side which is optimum for a PCB component arrangement.

Thus, it is also possible to carry out an optimization:

The package has been described as the package substrate. In some cases,furthermore, this is sealed with a resin. In some cases in which theresin sealing is carried out, however, it is necessary to take adielectric constant of the resin into consideration in the optimization.

According to the invention, it is possible to carry out a design with ahigh precision at a high speed by performing a design of a package to adesign of an LSI, that is, from a downstream side to an upstream sidebased on information about a semiconductor integrated circuit mountingsubstrate. Consequently, the invention can be applied to variousproducts including a communicating apparatus such as a cell phone,general household articles, toys and cars.

1-77. (canceled)
 78. A method of designing a semiconductor integratedcircuit comprising steps of: inputting design data of a packagesubstrate that connects a semiconductor integrated circuit; designing,via an apparatus for designing the semiconductor integrated circuit, aninput/output pad arrangement of the semiconductor integrated circuitbased on the inputted design data of the package substrate; andoutputting design data of the designed input/output pad arrangement ofthe semiconductor integrated circuit.
 79. The method of designing asemiconductor integrated circuit according to claim 78, furthercomprising, after the step of designing the input/output padarrangement, steps of: modifying the design data of the designedinput/output pad arrangement of the semiconductor integrated circuit;and correcting the input/output pad arrangement by using the modifieddesign data.
 80. The method of designing a semiconductor integratedcircuit according to claim 78, wherein the step of designing theinput/output pad arrangement comprises the step of designing thearrangement of the input/output pad of the semiconductor integratedcircuit corresponding to an arrangement of an external connectingterminal of the package substrate.
 81. The method of designing asemiconductor integrated circuit according to claim 78, wherein the stepof designing the input/output pad arrangement comprises the step ofdesigning the arrangement of the input/output pad of the semiconductorintegrated circuit corresponding to an arrangement of a component of thepackage substrate.
 82. The method of designing a semiconductorintegrated circuit according to claim 81, wherein the step of designingthe input/output pad arrangement comprises the step of carrying out adesign in such a manner that a wiring from the package substrate to theinput/output pad of the semiconductor integrated circuit does not havean intersecting region.
 83. The method of designing a semiconductorintegrated circuit according to claim 78, wherein the step of designingthe input/output pad arrangement comprises the step of carrying out adesign in order to determine a driving capability of an input/outputcell to be connected to the input/output pad of the semiconductorintegrated circuit corresponding to an arrangement of a component of thepackage substrate.
 84. An apparatus for designing a semiconductorintegrated circuit, wherein the apparatus receives as an input designdata of a package substrate that connects a semiconductor integratedcircuit, designs input/output pad arrangement of the semiconductorintegrated circuit based on the inputted design data of the packagesubstrate, and outputs design data of the designed input/out padarrangement of the semiconductor integrated circuit.
 85. The apparatusfor designing a semiconductor integrated circuit according to claim 84,wherein the apparatus modifies the design data of the designedinput/output pad arrangement of the semiconductor integrated circuit,and corrects the input/output pad arrangement by using the modifieddesign data as input data.
 86. The apparatus for designing asemiconductor integrated circuit according to claim 84, wherein theapparatus designs the arrangement of the input/output pad of thesemiconductor integrated circuit corresponding to an arrangement of anexternal connecting terminal of the package substrate.
 87. The apparatusfor designing a semiconductor integrated circuit according to claim 84,wherein the apparatus designs the arrangement of the input/output pad ofthe semiconductor integrated circuit corresponding to an arrangement ofa component of the package substrate.
 88. The apparatus for designing asemiconductor integrated circuit according to claim 84, wherein theapparatus determines a driving capability of an input/output cell to beconnected to the input/output pad of the semiconductor integratedcircuit corresponding to an arrangement of a component of the packagesubstrate.
 89. The apparatus for designing a semiconductor integratedcircuit according to claim 84, wherein the apparatus designs in such amanner that a wiring from the package substrate to the input/output padof the semiconductor integrated circuit does not have an intersectingregion, corresponding to an arrangement of a component of the packagesubstrate.
 90. A semiconductor integrated circuit that is mounted on asemiconductor integrated circuit mounting substrate and connected to apackage substrate, the semiconductor integrated circuit comprising: aninput/output pad; wherein the input/output pad is arranged correspondingto a position on the package substrate on which a component is arranged.91. The semiconductor integrated circuit according to claim 90, whereinthe input/output pad is arranged corresponding to an arrangement of anexternal connecting terminal of the package substrate.
 92. Thesemiconductor integrated circuit according to claim 90, wherein theinput/output pad is arranged corresponding to a position on the packagesubstrate on which a ball is arranged.
 93. The semiconductor integratedcircuit according to claim 90, wherein the input/output pad is arrangedcorresponding to a position on the package substrate on which anoutput/input cell is arranged.
 94. The semiconductor integrated circuitaccording to claim 90, wherein the input/output pad is arrangedcorresponding to a position on the package substrate on which a powercell is arranged.
 95. The semiconductor integrated circuit according toclaim 90, wherein the input/output pad is arranged corresponding to adriving capability of an input/output cell to be connected to theinput/output pad of the semiconductor integrated circuit.
 96. Thesemiconductor integrated circuit according to claim 90, wherein a wiringfrom the package substrate to the input/output pad of the semiconductorintegrated circuit does not have an intersecting region.